module vtest1(
    input a,
    input [15:0] in16,
    input [31:0] in32,
    input [63:0] in64,
    input [65:0] largeInput,
    output b,
    output [15:0] out16,
    output [31:0] out32,
    output [63:0] out64,
    output [80:0] largOutput
);

assign b = a;

endmodule